1. Technical Field
The present invention relates to a data output circuit of a semiconductor memory apparatus, and in particular, to a data output circuit of a semiconductor memory apparatus by which the number of semiconductor memory chips testable by one piece of test equipment can be increased.
2. Related Art
In general, a semiconductor memory apparatus includes a plurality of data output pads through which data is output to the outside of a semiconductor memory chip. When the semiconductor memory apparatus is tested, the data is transmitted to test equipment through data output lines that are respectively connected to the plurality of data output pads. Here, depending on a test mode of the semiconductor memory apparatus, various kinds of test equipment may be used. At this time, the number of data output lines that can be connected to test equipment is limited. Accordingly, the number of semiconductor memory chips that each piece of test equipment can test at once is also limited, which is directly related to efficiency when the semiconductor memory apparatus is tested.
Hereinafter, a data output circuit according to the related art will be described with reference to FIG. 1.
FIG. 1 is a view illustrating an example in which a data output circuit of a semiconductor memory apparatus according to the related art is used.
In FIG. 1, even though first and second semiconductor memory chips 10 and 20 each have four output lines, an actual semiconductor memory chip is not limited thereto.
As shown in FIG. 1, each of the first and second semiconductor memory chips 10 and 20 has four data output pads, and data output from each of the data output pads is input to test equipment 50 through each of the data output lines 60. Assuming that only eight data output lines 60 can be connected to the test equipment 50, the test equipment 50 can test only two semiconductor memory chips at once. Accordingly, at least five tests should be performed in order to test ten semiconductor memory chips each having four data output lines.
As described above, in the related art, since only data from one output pad is output from each of the data output lines connected to the test equipment, the number of semiconductor memory chips that can be tested by one piece of test equipment is limited. As a result, the test efficiency is poor.